verilog code and testbench for 4 bit updown counter which increments its value by 2 if count2=1 else it increments on decrements by 1 if updown=1

Verilog Code

module counter(Resetn,clock,En,count2,updown, Q);
    input Resetn,clock,En,count2,updown;
    output reg [3:0] Q;

always @( negedge Resetn, posedge clock)
 if (!Resetn)
  Q<=0;
else if (En)
  if( count2)  //if count2=1 then Q=Q+2
Q<= Q+2'b10;
  else if (updown) //if count2=0 then Q<=Q+1 if updown=1 else Q<=Q-1 if updown=0;
Q<=Q+1;
  else
Q<=Q-1;

endmodule

Test_bench

module tb_v;

// Inputs
reg Resetn;
reg clock;
reg En;
reg count2;
reg updown;

// Outputs
wire [3:0] Q;

// Instantiate the Unit Under Test (UUT)
counter uut (
.Resetn(Resetn),
.clock(clock),
.En(En),
.count2(count2),
.updown(updown),
.Q(Q)
);

initial begin
// Initialize Inputs
Resetn = 0;
clock = 0;
En = 1'b1;
count2 = 1'b1;
updown = 0;

// Wait 100 ns for global reset to finish
#100;
       
// Add stimulus here

end
always # 5 clock=~clock;
always # 100 updown =~updown;
always # 400 Resetn=~Resetn;
always # 80 count2=~count2;

   
endmodule